1. Field of the Invention
The present invention relates to, for example, a nonvolatile semiconductor memory device having a stacked gate comprising a floating gate and a control gate.
2. Description of the Related Art
A NAND-type nonvolatile semiconductor memory device is known as an example of a nonvolatile semiconductor memory device having a stacked gate. The NAND-type nonvolatile semiconductor memory device comprises a plurality of series-connected memory cells, and selection transistors which are connected to a drain side and a source side of the series-connected memory cells. A bit line contact electrode, which is electrically connected to a bit line, and a source line contact electrode, which is electrically connected to a source line, are arranged in the vicinity of the selection transistors.
The gate electrode of each memory cell has a stacked gate electrode structure comprising a floating gate electrode and a control gate electrode which is formed on the floating gate electrode via an inter-gate insulation film. The gate electrode of the selection transistor has a structure similar to the structure of the gate electrode of the memory cell. However, a part of the inter-gate insulation film is removed, and the floating gate electrode and the control gate electrode are electrically connected.
To reduce the resistance of the control gate electrode, an upper part of the control gate electrode is formed of a silicide layer and a lower part of the control gate electrode is formed of a silicon layer (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2000-311992). A similar structure is applied to the selection transistor, and a silicide layer is formed at the upper part of the gate electrode thereof. In addition, a lower part of the gate electrode is formed of a silicon layer, and that part of the gate electrode, which is in contact with the gate insulation film, is a silicon layer.
However, in the case where only the upper part of the control gate electrode is silicided and the silicon layer is left above the upper part of the floating gate electrode, a depletion layer occurs in the control gate electrode. Consequently, the capacitance of the inter-gate insulation film decreases by a degree corresponding to the depletion layer. Thus, such a problem arises that the coupling ratio of memory cells decreases and the characteristics of memory cells deteriorate. Accordingly, a nonvolatile semiconductor memory device has been desired which can suppress a decrease in coupling ratio of memory cells, and improving the characteristics of memory cells.